1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
2. Related Art
In recent years, the semiconductor device with a fuse is energetically developed with the objective of an improvement of reliability and manufacturing stability of the semiconductor device. As this kind of technique, there is one described in the Japanese Laid-Open Patent Publication No. 2003-209173. FIG. 16 is a schematic sectional view showing the conventional fuse structure described in the Japanese Laid-Open Patent Publication No. 2003-209173.
The fuse structure is comprised of a circuit portion 2120 having a multilayered interconnect structure and a fuse portion 2110 including a plurality of fuses 220, which are irradiated with a laser beam and melted by an irradiation of the laser beam. The circuit portion 2120 and the fuse portion 2110 both are formed on a silicon substrate 210.
Interlayer insulating films 232, 234, 236 and 238 composed of a silicon oxide film or the like are formed on the silicon substrate 210 in this order from the silicon substrate 210 side. A first protective layer 240 and a second protective layer 242 composed of a silicon nitride film or the like are formed between the interlayer insulating film 236 and the interlayer insulating film 238. Pluralities of fuses 220 are formed between the first protective layer 240 and the second protective layer 242. A passivation film 280 composed of the silicon nitride film or the like is further formed on the interlayer insulating film 238.
The circuit portion 2120 is provided with interconnect layers 260, 270. Transistors composed memories or the like or another elements (not shown in the drawings) are connected to the interconnect layers 260, 270. The interconnect layer 260 is formed on the interlayer insulating film 234. The interconnect layer 270 is formed on the second protective layer 242.
The plurality of fuses 220 is provided on the second protective layer 242 in the fuse portion 2110. A plurality of an interconnect layer 250 is provided on an element isolation region 212. The fuse portion 2110 provided with an opening 216 of the passivation film 280.
According to the Japanese Laid-Open Patent Publication No. 2003-209173, there is described that, based on this configuration, in the case where the fuse is melted by the irradiation of the laser beam, it is possible to suppress intrusion of moisture or impurity upon providing the first protective layer 240 and the second protective layer 242 above and below the fuse 220 respectively.
On the other hand, there is the Japanese Laid-Open Patent Publication No. 2003-086590, which differs from the semiconductor device according to the present embodiment in the technical field, disclosing the seal ring structure surrounding a semiconductor element with the objective of suppressing intrusion of moisture or impurity. The Japanese Laid-Open Patent Publication No. 2003-086590 describes of providing the seal ring between the memory portion and the fuse portion so as to surround the memory portion. There will be described about the Japanese Laid-Open Patent Publication No. 2003-086590 later is detail.